In a new announcement, IBM touted a zEC12 as a initial commercially accessible appurtenance to
support transactional memory by a doing of Transaction Execution Facility
Transactional memory potion half full
Normal mainframe serialization relies on enqueues, latches and locks. At a machine-code level,
Z systems offer instructions such as
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. Besides being complex, these mechanisms share a integrate of unattractive side effects. A
program that fails to get tenure of a apparatus customarily waits, that can lead to elongated
response times and cascading hangs. If programmers aren’t careful, a normal methods are also
prone to deadly
that henceforth retard during slightest dual processes until one is canceled.
In contrast, TEF employs an “optimistic” opinion that assumes it can ensue though conflicts.
If a confidence is misplaced, a hardware rolls a transaction behind and lets a module decide
what to do next.
The zEC12 combined dual special machine instructions
to symbol a commencement and finish of transactions. In between these instructions, a module can load
and store from memory and change registers. However, all a changes are provisional and uncommitted
until a routine ends a transaction though encountering a conflict. If a dispute arises — for
instance if another CPU changes a memory plcae referenced by a transactional routine — the
hardware aborts a transaction, including changes to memory, and a whole thing has to start
over. Note that programs regulating TEF contingency heed to a specific entrance proof since if a conflict
causes a CPU to miscarry a process, it will bend behind to a instruction immediately
following a commencement of a transaction, afterwards set a non-zero condition formula (CC).
In addition, a zEC12 supports compelled transactions. Constrained exchange have a few
restrictions as to what they can do though they’re some-more expected to succeed.
Non-constrained exchange can be nested adult to a indication contingent depth. The processor commits
the changes as any transaction ends. However, if a dispute arises, a cancel goes all a way
back to a utmost transaction.
Programmers competence use a ETND instruction to get a transaction nesting depth.
If a CPU isn’t in transactional mode, a nesting abyss is zero.
The TEF instructions
These are a new instructions creation adult a TEF:
The Transaction Diagnostic Block
A programmer competence optionally mention a 256-byte area for a transaction evidence retard (TDB) to
receive CPU-generated dispute data. The TDB contains a lot of information, including a general
registers during a time of a dispute along with a transaction cancel code.
The zEC12 Principle of
Operations sum a many reasons because a transaction competence be aborted. The POPS also warns
that conflicts can arise from “speculative” instruction examination, that is partial of out-of-order
instruction execution. This creates interesting, Kafkaesque situations where a transaction will be
aborted for something that competence or competence not have happened.
A closer demeanour during TEF
Below is a formula TEF formula fragment:
XR R2,R2 Clear a loop counter
TBEGIN X’FF00′,TDB Transaction begin
JNZ TRANABRT JMP if formerly aborted
AP TRANCNT,=P’1′ Increment decimal counter
TEND Commit changes
J ITWORKED Move on to improved things
TDB DS XL256 Diagnostic area
TRANABRT DS 0H
LA R2,1(,R2) Increment loop counter
CHI R2,=H’30′ 31st time through?
JL TRANSTRT No, retry transaction
PLANB DS 0H Yes, try something
These instructions try to increment a packaged decimal opposite in common storage. The proof will
try to refurbish a opposite 30 times before giving up.
The initial instruction clears register dual (R2), that keeps lane of a series of update
attempts. The subsequent instruction, TBEGIN, puts a CPU in transactional state. The TBEGIN’s first
operand is a facade that tells a processor to revive a essence of ubiquitous purpose registers 0
through 15 if something aborts a transaction. This is critical as a R2 contains a loop
counter. The second operand points to a TDB.
This is where a transaction entrance proof becomes important. The instruction after a TBEGIN
tests a CC. If a CC is zero, a processor was successfully put into transactional state and
control falls by to refurbish a counter. A non-zero CC means something aborted a transaction
and caused a bend to a liberation proof during tag TRANABRT.
After — hopefully — updating a counter, a TEND instruction ends a transaction and
commits a incremented counter.
The instructions following TRANABRT try to redeem from an aborted transaction. First, it
increments a value in R2. If a value is reduction than 30, it jumps behind to re-initialize the
transaction. Otherwise it falls by to devise B.
TEF appears to be a jump brazen in processor
technology , deliberation a formidable electronics and microcode indispensable to guard memory and
generate interrupts. The doubt is if it is easier or some-more fit than some of a other
methods mentioned above.
Although a above instance is contrived, it can offer as a approach to consider about how TEF works on a
busy system. Given that a supplement packaged (AP) instruction would govern in nanoseconds, chances are
better than good a transaction will work a initial time even while dozen of threads competence wish to
update that counter. In this case, TEF appears to be a flattering easy solution.
Chances are TEF will find a approach into lots of system-level code. However, IBM also intends
customers to use it by a new Java and C++
About a expert:
Robert Crawford has been a systems programmer for 29 years. While specializing in CICS technical
support, he has also worked with VSAM, DB2, IMS and other mainframe products. He has automatic in
Assembler, Rexx, C, C++, PL/1 and COBOL. In his latest career proviso he is an operations architect
responsible for substantiating mainframe plan and instruction for a vast word company. He
works in south Texas, where he lives with his family.
This was initial published in Nov 2012
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